This invention relates generally to CMOS static random access memories and more particularly, it relates to an improved CMOS precharge and equalization circuit for use with CMOS memory cells which are coupled between differential paired bit lines.
In general, in CMOS static random access memories there are a plurality of memory cells which are arranged in an array forming columns of bits and rows of words where each memory cell is disposed for storing and retrieving binary information. Each memory cell may be comprised of a MOS cross-coupled latch (two inverters connected back-to-back) and a pair of coupling transistors coupled between the latch and a common set of interconnect lines. Since these interconnect lines are differential in nature, they are typically referred to as bit lines, which are used as a means for both writing information into the memory cell and sensing (reading) information from the memory cell via a differential read/write port.
As is well known in the art, sense amplifiers are used to detect or sense the binary state of one of the memory cells in the column of memory cells arranged between the differential bit lines. As memories become more and more dense, each of the columns is coupled with a higher number of memory cells. As a result, the pairs of bit lines become relatively long conductors which represent a relatively large capacitive load. The MOS latches are ordinarily not capable of providing a high current so as to charge up or discharge rapidly the capacitive load of the bit lines. Consequently, more time is required to charge and discharge the parasitic capacitive loads, thereby increasing write and read times to and from the memory cells.
Prior art solutions to this problem involves the provision of precharge and equalization circuits for precharging the bit lines to a particular value. As used herein, "precharge" defines the charging of a node to a specified voltage level and "equalization" defines the process of sharing charge between two nodes to insure an equal voltage level therebetween. Therefore, it can be seen that an important aspect of memory design is determining the voltage level to which the differential bit lines are precharged. The particular voltage level of the pairs of bit lines is an important consideration due to the characteristics of the memory cell and sensitivity of the sense amplifier.
In a cross-coupled pair sense amplifier, the amplifier feeds back to the bit lines. This is typically necessary to restore data in the selected memory cell. The amplifier senses small voltage differentials on the pair of bit lines and begins to further increase the voltage differential. In the usual practice, the precharge and equalization circuit is used to precharge and equalize the bit lines in a precharge cycle prior to a read cycle. That is, the differential bit lines must have null data on them. If the differential bit lines are not equalized properly, residual data on the bit lines may be transferred to the memory cell during the reading process, thereby destroying memory cell data. In such instance, the small voltage differential on the bit lines would be transferred to the memory cell and amplified therein. Thus, some form of precharge and equalization circuit is generally required for the proper operation of the memory.
In FIGS. 1a and 1b, there are shown two different prior art precharge and equalization circuits which are used to precharge or set the differential bit lines BL and BL to a predefined voltage level. The circuit 10a of FIG. 1a includes a first N-channel precharge transistor N1, a second N-channel precharge transistor N2, and an equalization P-channel P1. Ideally, the precharge voltage will be set on the respective bit lines (source electrodes of the transistors N1 and N2) at a threshold drop V.sub.Tn below the supply potential VCC or V.sub.pre =VCC-V.sub.Tn, where V.sub.Tn is a body-effect enhanced threshold. The supply potential VCC is typically at +5.0 volts, and the threshold drop V.sub.Tn varies between 0.6 and 0.9 volts. However, in actual practice the transistors N1 and N2 will tend to leak so that the voltage on the bit lines BL and BL may be charged to the full value of the supply potential VCC. In order to prevent the bit lines from charging all the way up to the supply potential VCC, a bleeder circuit 12a is usually added on each bit line so as to leak charge away from the bit lines. The bleeder circuit 12 is quite conventional and is generally formed of a polyresistor or an active device. Thus, this leakage of charge serves to insure that the precharge voltage will be maintained approximately at the VCC-V.sub.Tn level.
Similarly, the circuit 10b of FIG. 1b includes a first P-channel precharge transistor P2, a second P-channel precharge transistor P3, and an equalization N-channel transistor N3. Again, a bleeder circuit 12b is usually added on each bit line so as to prevent them from charging down to the supply potential VSS. As a result, the precharge voltage will be maintained approximately at a threshold drop V.sub.Tp above the supply potential VSS or V.sub.pre =VSS+V.sub.Tp. The supply potential VSS is typically at 0 volts, and the threshold drop varies between -0.6 and 0.9 volts.
It will be understood that in a standard random access memory array there would be additional bit line pairs or columns, each bit line in each of the columns being coupled to a bleeder circuit 12a or 12b similar to that shown in respective FIGS. 1a and 1b. For example, there may be 32 or 64 columns so as to form a 32-bit or 64-bit word. Further, each column may contain any number of bit memory cells connected between the corresponding paired bit lines. There may be perhaps 128 or 256 or more of these memory cells connected between each paired bit line so as to form 128 or 256 different words.
However, the inclusion of a bleeder circuit coupled to each bit line for all of the columns in a static random access memory array increases greatly the size of the integrated circuit and adds to the complexity of the memory. In view of this, there exists a need for an improved precharge and equalization circuit for precharging the bit lines in a static random access memory array without requiring the use of bleeder circuits. It should be noted that by eliminating of bleeder circuits there is realized a savings of power consumption. Further, the elimination of the bleeder circuits from each of the differential paired bit lines will provide reduced bit line capacitance, thereby effecting faster READ and WRITE operations.